1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to a method for generally simultaneously fabricating a plurality of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have first-type features and other selected ones of the shallow trench isolation structures have second-type features.
2. Description of Related Art
Integrated circuits are well known. Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, so as to increase the density of the individual components thereof and consequently enhance the functionality of an integrated circuit.
For example, there is a strong desire to reduce the size of the integrated circuits used to make memory chips. By reducing the size of the integrated circuits, each memory chip can have more capacity and thus be more functional.
However, the greater semiconductor component densities which result from such miniaturization inherently result in an increased potential for undesirable electrical interactions between nearby components.
For example, undesirable parasitic inter-device currents tend to be accentuated as semiconductor component densities increase. Such parasitic inter-device currents can occur when carriers, such as either electrons or electron holes, drift between adjacent active devices on a semiconductor substrate. Such drifting of carriers becomes more pronounced as the distance between active devices decreases.
Thus, in the fabrication of integrated circuits, it is frequently necessary to isolate the semiconductor components from one another, so as to mitigate the potential for such undesirable electrical interactions.
A widely used technology for isolating adjacent metal oxide semiconductor (MOS) circuits involves the local oxidation of silicon (LOCOS), in which unmasked non-active or field regions of the silicon substrate are exposed to a heated oxidizing atmosphere to thereby grow recessed or semi-recessed silicon dioxide (e.g., field oxide) areas. The silicon dioxide on the unmasked regions is generally grown thick enough to lower any parasitic capacitance which may occur over the regions of interest, but not so thick as to cause step coverage problems. As distinguished from non-active regions, regions of the substrate that are to be fabricated as active regions are protected by masking to facilitate the subsequent formation of active devices in the active regions.
However, LOCOS isolation applications are not without limitations. For example, a commonly recognized limitation is that of oxide undergrowth at the edge of the mask, wherein the silicon dioxide being grown intrudes laterally under the edge of the mask and encroaches into the active regions of the substrate. This phenomenon, which is commonly known as “bird's beak,” can adversely affect device performance, reduce the area in which active devices can be built, and create stress in the substrate, while not appreciably contributing to device isolation. Moreover, as the oxide grows under the mask, the mask layer is undesirably pushed up forming a non-planar oxide defect. This non-planar defect stems, in part, from the fact that the thermally grown oxide can have approximately twice the thickness of the silicon consumed in the thermal oxidation process. Resulting non-planar formations can present problems with, for example, subsequent layer conformity and photolithography.
Recognizing the shortcomings of LOCOS isolation implementations, contemporary complimentary metal oxide semiconductor (CMOS) constructions have increasingly utilized trenches, and in particular shallow trench isolation (STI) structures, between active regions. Shallow trench isolation structure formation typically entails using a mask to define and pattern a shallow trench on a substrate using anisotropic etching processes, and then filling the shallow trench with an insulating material, followed by a subsequent step wherein the insulating material is planarized back to define the shallow trench isolation. Shallow trench isolation structures can attenuate or eliminate the “bird beak” problem of oxide intrusion into active areas, thus allowing for greater operability and smaller isolation element spacing.
Regarding shallow trench isolation structures, it may in some circumstances be desirable to form them to have different dimensions (e.g., sizes and shapes) at different locations on a substrate. In a memory device, for example, the operation voltage in a periphery region is typically higher than the operation voltage in a cell region. Therefore, if may be desirable to form shallow trench isolation structures in the periphery region to be deeper and larger than shallow trench isolation structures in the cell region.
Shallow trench isolation structures typically comprise abruptly-shaped sides and corners, as a result of, for example, the anisotropic etching methods which are used to form the trench isolations. These abrupt geometries may lead to undesirable electrical characteristics, such as “edge conduction” wherein excessive current leakage occurs in the upper region between the top of an isolation trench and an adjacent active device. An active device disposed in close proximity to a small-radius edge or corner of an isolation trench may exhibit, for example, a relatively high edge conduction including undesirable parasitic leakage paths. Such undesirable effects as the well known double hump of the characteristic I-V curve (see U.S. Pat. No. 6,074,931) of an active device can result.
Additionally, the sharp corners of the shallow trench isolation can also lead to difficulties in depositing the trench with dielectric filler material during subsequent processing. For example, sharp corners at the upper opening of the trench can lead to a pinching-off of that opening of the trench during dielectric deposition before the trench is completely filled, leaving an undesirable void in the trench filling. As the trend continues for component miniaturization and device density, it becomes more and more desirable to form narrower deep trench isolations having larger aspect ratios. The problem of void formation, however, can be exacerbated as the aspect ratio of the trench isolation is increased.
For example, as isolation trenches are formed with greater aspect ratios, it becomes increasingly probable that, during the filling of the isolation trench with silicon dioxide, narrowing of the opening at the mouth of the trench from the formation of the silicon dioxide will impede proper and complete filling of the trench resulting in the formation of voids.
Rounding of the corners or edges of a shallow trench isolation structure tends to mitigate at least some of the aforementioned problems associated with sharp corners thereof. However, although it is desirable to round the corners of a shallow trench isolation structure in some instances, in other instances it may not be possible, practical, or desirable to do so.
For example, in memory devices the critical dimension, i.e., the width, of the shallow trench isolation structures in the cell region is typically smaller than the critical dimension of the shallow trench isolation structures in the periphery region. Although it may be desirable to round the corners of the shallow trench isolation structures in the periphery region of the memory device to mitigate the double hump in the characteristic I-V curve thereof, this cannot be accomplished while maintaining the relatively small critical dimension of the shallow trench isolation structures in the cell region.
In this instance, corner rounding can necessitate an unacceptable reduction in the critical dimension of the shallow trench isolation structures in the cell region. Further, as discussed above, it can be relatively difficult to properly fill a shallow trench isolation structure having such a reduced critical dimension with insulating material. Thus, in this instance, it is necessary or desirable to leave the shallow trench isolation structures of the cell region unrounded.
However, it is still desirable to round the corners of the shallow trench isolation structures in the periphery of the memory device for the aforementioned reasons. Thus, it is desirable to form an integrated circuit such that some of the shallow trench isolation structures thereof have rounded corners and others of the shallow trench isolation structures thereof have unrounded corners. Of course, forming the shallow trench isolation structures having rounded corners using a different process from that used to form the shallow trench isolation structures having unrounded corners would be undesirably inefficient, costly, and likely to adversely affect yield.
A need thus exists in the prior art for methods of simultaneously forming shallow trench isolation structures having varying dimensions, such as varying sizes and shapes, in accordance with their respective locations on a substrate.